• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A process for forming a final passivation layer over an integrated circuit comprises a step of forming, over a surface of the integrated circuit, a protective film by means of High-Density Plasma Chemical Vapor Deposition.
    公开号:US20010001727A1
    申请号:US09/060,192
    申请日:1998-04-14
    公开日:2001-05-24
    发明作者:Giorgio De Santi；Luca Zanotti
    申请人:SGS Thomson Microelectronics SRL；
    IPC主号:H01L21-02164
    专利说明:
    [0001] The present invention relates to a process of forming final passivation of an integrated circuit device and a device made by said process. [0001] BACKGROUND OF THE INVENTION
    [0002] Semiconductor integrated circuits manufactured with Large Scale of Integration (LSI) technologies (LSI, VLSI, ULSI) require a protective layer against mechanical stress and aggressive chemical agents. This layer, generally called “passivation layer,” is typically formed by silicon-based dielectrics, such as silicon dioxide (USG), phosphorus-doped or fluorurate-doped silicon oxide (PSG or FSG), silicon nitrides and nitride oxides (Si[0002] 3N4, SiOxN).
    [0003] The passivation layer is conventionally formed by means of Chemical Vapor Deposition (CVD) techniques, either Plasma-Enhanced (PECVD) or at Atmospheric Pressure (APCVD). [0003]
    [0004] Final passivation layers formed by means of the above-referred conventional techniques have up to now proved to be sufficiently satisfactory, and in view of the relatively low cost of both PECVD and APCVD manufacturing equipment their use has never been disputed. [0004]
    [0005] On the other hand, a new CVD technique has been known for some years for the formation of Inter-Metal Dielectric (IMD) protective films in ULSI circuits. Such a technique, called High-Density Plasma CVD (HDPCVD), is substantially a combination of two simultaneous processes, i.e., deposition and sputtering. [0005]
    [0006] The advantage of HDPCVD over known alternative IMD film formation processes (such as PECVD, APCVD or Spin-On-Glass (SOG) processes) is that this technique allows for better (complete) filling of gaps between metal lines, even for sub-micrometric intra-metal line distances, of the integrated circuit. [0006] SUMMARY OF THE INVENTION
    [0007] To resolve the difficulties of conventional techniques, an object of the present invention is to provide a new process of final passivation of integrated circuits by means of which final passivation layers having improved characteristics over conventionally-formed passivation layers can be formed, particularly suitable where the scale of integration of the integrated circuits is increased. [0007]
    [0008] One embodiment of the present invention includes a method for forming a final passivation layer over an integrated circuit, characterized by comprising a step of forming, over a surface of the integrated circuit, a protective film by means of High-Density Plasma Chemical Vapor Deposition technique. [0008]
    [0009] By applying the present invention, it is possible to form passivation layers with improved step coverage characteristics, even for extremely small geometries, for the integrated circuits. The resulting passivation layer of the integrated circuit does not depend, for example, on the distance between the metal lines of an upper metal layer of the integrated circuit even if such a distance is as low as approximately 0.2 μm. Additionally, the gaps between said metal lines are completely filled by the passivation layer. [0009]
    [0010] Said protective film can be made of silicon dioxide, phosphorus-doped or fluorurate-doped silicon oxide, silicon nitrides or oxinitrides, and other suitable materials having a low dielectric constant. [0010]
    [0011] The passivation layer may further comprise other films in addition to the one formed by means of HDPCVD. For example, these other films may be formed by means of PECVD or APCVD techniques. In this case, a first passivation film is formed over the surface of the integrated circuit to be protected by means of HDPCVD, thus filling completely the gaps between the metal lines defined in the uppermost metal layer of the integrated circuit. Over said first film, other passivation films are formed by means of conventional PECVD or APCVD techniques. [0011]
    [0012] It has been realized and practically verified by Applicant that, notwithstanding the present common technical prejudice in favor of PECVD- or APCVD-formed final passivation layers, the conventional PECVD or APCVD techniques could no longer provide satisfactory results as the integration scale of integrated devices is increased and the present invention provides considerable advantages. [0012]
    [0013] The features and advantages of the present invention will be made apparent from the following detailed description of a particular embodiment thereof, illustrated as a non-limiting example in annexed drawings. [0013] BRIEF DESCRIPTION OF THE DRAWINGS
    [0014] FIG. 1 is a schematic cross-sectional view of a portion of an integrated circuit before the formation of the final passivation layer. [0014]
    [0015] FIG. 2 shows the portion of integrated circuit of FIG. 1, after a final passivation layer has been formed by means of a process according to the invention. [0015]
    [0016] FIG. 3 shows an additional layer deposited over the passivation layer according to the invention. [0016] DETAILED DESCRIPTION OF THE INVENTION
    [0017] In FIG. 1, a portion of an integrated circuit chip [0017] 3 is schematically shown in cross-section. The chip 3 generically comprises a substrate 4, over which, e.g., metal lines 2 are formed and between the metal lines 2, gaps 1 are formed. If the integrated circuit is fabricated by means of an Ultra Large Scale of Integration (ULSI) process, the gaps 1 can be as narrow as approximately 0.2 μm.
    [0018] The integrated circuit chip [0018] 3 is to be protected by means of a final passivation layer.
    [0019] According to an embodiment of the present invention, said final passivation layer is a dielectric layer of undoped silicon dioxide deposited over the surface of the integrated circuit chip [0019] 3 by means of High Density Plasma Chemical Vapor Deposition (HDPCVD). The chip (actually, the whole semiconductor wafer to which the chip belongs) is introduced in a CVD reaction chamber wherein the following process conditions are preferably provided:
    [0020] O[0020] 2, SiH4, Ar gas flow between 5-150 sccm, for each gas;
    [0021] 2000 to 4000 W source Radio-Frequency (RF) power; [0021]
    [0022] a reaction chamber pressure of less than 10 mTorr; and [0022]
    [0023] a 2.5:1 to 8.0:1 deposition/sputtering ratio. [0023]
    [0024] At the end of this process, a passivation layer [0024] 5 covers the integrated circuit, as schematically shown in FIG. 2. It is to be noted that the passivation layer 5 completely fills the gaps I between the metal lines, even if such gaps are as narrow as approximately 0.2 μm.
    [0025] Even if the above example has been referred to the formation of a silicon dioxide passivation layer, other materials, for example, phosphorus-doped or fluorurate-doped silicon oxide (PSG or FSG), silicon nitrides and nitride oxides (Si[0025] 3N4, SiOxNy) can as well be deposited by means of HDPCVD.
    [0026] In an alternative embodiment, the passivation layer could also comprise a stack of layers, the lowermost formed by means of HDPCVD technique, and the superimposed layers may be formed by conventional PECVD or APCVD techniques. In FIG. 3, an additional layer [0026] 6 formed by PECVD or APCVD is shown being superimposed over the passivation layer 5. In this way, the lowermost, HDPCVD deposited layer allows for a complete filling of the gaps.
    [0027] From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims. [0027]
    权利要求:
    Claims (12)
    [1" id="US-20010001727-A1-CLM-00001] 1. A method for forming a final passivation layer over an integrated circuit, the method comprising a step of forming, over a surface of the integrated circuit, a first protective film by means of High-Density Plasma Chemical Vapor Deposition.
    [2" id="US-20010001727-A1-CLM-00002] 2. The method of claim I wherein said High-Density Plasma Chemical Vapor Deposition comprises the following steps:
    placing the integrated circuit into a reaction chamber;
    providing a mixture of a dielectric material gas and an inert gas with a gas flow in between 5 to 150 sccm within the reaction chamber, for each gas;
    providing a radio-frequency source of power at about 2000 to about 4000 watts within the reaction chamber;
    providing a reaction chamber pressure of less than 10 mTorr; and
    depositing the passivation layer at a deposition/sputtering ratio of about 2.5:1 to about 8.0:1 to the integrated circuit.
    [3" id="US-20010001727-A1-CLM-00003] 3. The method of
    claim 2 wherein said dielectric material gas includes oxygen, or silicon hydride, or phosphorus, or fluorine, or nitrogen, or any combination thereof.
    [4" id="US-20010001727-A1-CLM-00004] 4. The method of
    claim 2 wherein said inert gas includes argon.
    [5" id="US-20010001727-A1-CLM-00005] 5. The method of
    claim 1 , further comprising a step of providing a second protective film over said first protective film.
    [6" id="US-20010001727-A1-CLM-00006] 6. The method of
    claim 5 wherein said second protective film is formed by Plasma-Enhanced Chemical Vapor Deposition (PECVD) or by Atmospheric Pressure Chemical Vapor Deposition (APCVD).
    [7" id="US-20010001727-A1-CLM-00007] 7. An integrated circuit device, comprising a passivation layer having a first dielectric film deposited by means of High-Density Plasma Chemical Vapor Deposition.
    [8" id="US-20010001727-A1-CLM-00008] 8. The device of
    claim 7 , further comprising a second dielectric film deposited over the first dielectric film and formed by Plasma-Enhanced CVD or by Atmospheric Pressure CVD.
    [9" id="US-20010001727-A1-CLM-00009] 9. A method for forming a final passivation layer having a first protective film over an integrated circuit, the method comprising:
    placing an integrated circuit into a reaction chamber;
    providing a mixture of a dielectric material gas and an inert gas within the reaction chamber;
    providing a radio-frequency source of power at about 2000 to about 4000 watts within the reaction chamber;
    providing a reaction chamber pressure of less than 10 mTorr; and
    depositing the first protective film of the passivation layer at a deposition/sputtering ratio of about 2.5:1 to about 8.0:1 to the integrated circuit.
    [10" id="US-20010001727-A1-CLM-00010] 10. The method of
    claim 9 wherein the dielectric material gas includes oxygen, or silicon hydride, or phosphorus, or fluorine, or nitrogen, or any combination thereof.
    [11" id="US-20010001727-A1-CLM-00011] 11. The method of
    claim 9 wherein said inert gas includes argon.
    [12" id="US-20010001727-A1-CLM-00012] 12. The method of
    claim 9 , further comprising a step of providing a second protective film over said first protective film.
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    同族专利:
    公开号 | 公开日
    EP0872879A1|1998-10-21|
    US20030122221A1|2003-07-03|
    US6888225B2|2005-05-03|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US10407247B2|2016-03-03|2019-09-10|Spaleck GmbH & Co. Kommanditgesellschaft|Vibratory conveyor with a conveyor trough which is made of a flexible mat|US4892753A|1986-12-19|1990-01-09|Applied Materials, Inc.|Process for PECVD of silicon oxide using TEOS decomposition|
    TW214599B|1990-10-15|1993-10-11|Seiko Epson Corp||
    EP0497541A1|1991-01-28|1992-08-05|Kawasaki Steel Corporation|Semiconductor device with a borophosphosilicate glass and method of manufacturing the same|
    US5250843A|1991-03-27|1993-10-05|Integrated System Assemblies Corp.|Multichip integrated circuit modules|
    JP3670277B2|1991-05-17|2005-07-13|ラムリサーチコーポレーション|Method for depositing SiOx films with low intrinsic stress and / or low hydrogen content|
    US5260236A|1991-06-07|1993-11-09|Intel Corporation|UV transparent oxynitride deposition in single wafer PECVD system|
    US5565247A|1991-08-30|1996-10-15|Canon Kabushiki Kaisha|Process for forming a functional deposited film|
    EP0560617A3|1992-03-13|1993-11-24|Kawasaki Steel Co|Method of manufacturing insulating film on semiconductor device and apparatus for carrying out the same|
    JP2950029B2|1992-07-23|1999-09-20|日本電気株式会社|Method for manufacturing semiconductor device|
    US5353498A|1993-02-08|1994-10-11|General Electric Company|Method for fabricating an integrated circuit module|
    US5614055A|1993-08-27|1997-03-25|Applied Materials, Inc.|High density plasma CVD and etching reactor|
    US5679606A|1995-12-27|1997-10-21|Taiwan Semiconductor Manufacturing Company, Ltd.|method of forming inter-metal-dielectric structure|
    US5641546A|1996-05-06|1997-06-24|Hughes Aircraft Company|Passivation of electronic modules using high density plasmas|
    US5804259A|1996-11-07|1998-09-08|Applied Materials, Inc.|Method and apparatus for depositing a multilayered low dielectric constant film|
    US6127285A|1997-02-28|2000-10-03|Dallas Instruments Incorporated|Interlevel dielectrics with reduced dielectric constant|
    US6117345A|1997-04-02|2000-09-12|United Microelectronics Corp.|High density plasma chemical vapor deposition process|
    EP0887847A1|1997-04-15|1998-12-30|STMicroelectronics S.r.l.|Process of final passivation of integrated circuit devices|
    US5814564A|1997-05-15|1998-09-29|Vanguard International Semiconductor Corporation|Etch back method to planarize an interlayer having a critical HDP-CVD deposition process|US8431473B2|2011-07-07|2013-04-30|United Microelectronics Corp.|Method for fabricating semiconductor device|
    法律状态:
    1998-07-23| AS| Assignment|Owner name: SGS-THOMSON MICROELECTRONICS S.R.L., ITALY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DE SANTI, GIORGIO;ZANOTTI, LUCA;REEL/FRAME:009349/0909 Effective date: 19980427 |
    2002-09-09| STCB| Information on status: application discontinuation|Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
    优先权:
    申请号 | 申请日 | 专利标题
    EP97830174.5||1997-04-15||
    EP97830174A|EP0872879A1|1997-04-15|1997-04-15|Process of final passivation of an integrated circuit device|US10/323,961| US6888225B2|1997-04-15|2002-12-18|Process of final passivation of an integrated circuit device|
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